SML2108
PRELIMINARY
TIMING DIAGRAMS
S
T
A
R
T
S
Data
Byte
n
Data
Byte
n+1
Data
T
Byte
O
Device
Address
R/
W
Master
SDA
n+15
P
x
0 1 0
x x
0
Word Address
1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Slave
2053 Fig14
Figure 14. Look-up Table Page/Byte Write
S
S
S
N
T
A
R
T
T
T
A
A
R
T
A
Device
Address
Device
Address
O
C
R/
W
R/
C
Master
SDA
P
K
W K
x
x
x
x x x
0
0
Word Address
1
Data Byte
1
0
1
0
1
0
1
A
C
K
A
C
K
2053 Fig15
Slave
Figure 15. Look-up Table Random Address Read with Dummy Write
S
T
A
R
S
S
T
O
P
T
A
R
T
First
Data
Byte
Last
Data
Byte
N
A
C
K
A
C
K
A
C
K
Device
Address
Device
Address
R/
W
R/
W
Master
T
x
x
x
x x x
0
0
Word Address
1
1
0
1
0
1
0
1
SDA
A
C
K
A
C
K
A
C
K
2053 Fig16
Slave
Figure 16. Look-up Table Sequential Read with Dummy Write
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
16
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
