SML2108
PRELIMINARY
BUS INTERFACE
GENERAL DESCRIPTION
The I2C bus is a two-way, two-line serial communication SDA line must be connected to a positive supply by a pull-
between different integrated circuits. The two lines are: a up resistor located on the bus. Summit parts have a
serial Data line (SDA) and a serial Clock line (SCL). All Schmitt input on both lines. See Figure X1 and Table X1
Summit Microelectronics parts support a 100kHz clock for waveforms and timing on the bus. One bit of Data is
rate, and some support the alternative 400kHz clock. transferred during each Clock pulse. The Data must
Check the AC Electrical Table for the value of fSCL. The remain stable when the Clock is high.
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:SDA
SU:DAT
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2053 Fig08
Figure 8. I2C Data Timing
Conditions
Symbol
Parameter
SCL clock frequency
Clock low period
Clock high period
Bus free time
Min.
0
Max.
Units
kHz
µs
fSCL
tLOW
tHIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
tAA
100
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
µs
Before new transmission
µs
Start condition setup time
Start condition hold time
Stop condition setup time
µs
µs
µs
Clock edge to valid output
Data Out hold time
SCL low to valid SDA (cycle n)
3.5
µs
tDH
SCL low (cycle n+1) to SDA change
µs
tR
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
1000
300
ns
tF
ns
tSU:DAT
tHD:DAT
TI
250
0
ns
Data In hold time
ns
Noise filter SCL and SDA
Write cycle time
Noise suppression
100
5
ns
tWR
ms
2053 Table01 1.0
Table 1. I2C Data Timing
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
