SML2108
PRELIMINARY
REGISTERS
REGISTER BIT MAPS
reset by a low AUTOMON signal. Bit 5 is used to toggle
the source of the ADC input between the IBIAS current and
the EXT TEMP signal. Bit 2 initializes the input of the 10
bit DAC to either zero or a stored value from a nonvolatile
registerwhenthedeviceispoweredup. Bit1initializesthe
input of the 8 bit DAC to either zero or a stored value from
a nonvolatile register when the device is powered up. Bit
0 sets the maximum P-channel bias current (IBIASP) and
modulation current (IMODP) to either 10mA or 100mA.
The SML2108 has three user programmable, nonvolatile
configuration registers.
Register 0
This register is used to configure the 8-Bit ADC that
monitors the bias current. Bit 7 enables the ADC alert to
belatched,whichwillholdtheALERTpinlowuntilthealert
isreset. Bits6, 5, and4areusedtosetthesampleinterval
oftheADC. TheinputtotheADCcanbescaledandoffset
to provide maximum resolution over the bias current. Bits
3 and 2 are used to set the full scale range of the ADC,
while bits 1 and 0 are used to set the ADC offset. See the
Table.
Register 2
This register controls several functions related to the bus
interface. Bits 7 and 6 control the read and write access
to the configuration registers. It is imperative that register
2 be programmed properly to prevent an inadvertent
lockout. Bit 5 determines whether the memory array is
available or locked. Bit 4 selects the device type address
for accessing the memory array, while bit 3 determines
whether the device must receive a bus address that
corresponds to the biasing of the address pins. Bit 2 is
usedtoenableanalertconditionontheADCtoshutdown
the bias current. Bits 1 & 0 are unused.
Register 1
Thisregistercontrolsmultiplefunctions. Bit7disablesthe
alert during a manual analog-to-digital conversion of the
bias current. Bit 6 selects the action that will reset an alert
from the ADC. When this bit is set to a 0 any device read
or write will reset the alert. When set to a 1 the alert will be
7
6
5
4
3
2
1
0
Function
Alert not latched
ADC
Alert
ADC Sample Interval
ADC Range
ADC Offset
0
1
x
x
x
Alert latched
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5µs sample interval
20µs
"
"
160µs
1.28ms
6.25ms
25ms
200ms
1.6s
"
"
x
x
"
"
"
"
x
x
"
"
"
"
"
"
x
0
0
1
1
0
1
0
1
1/10 full scale bias current
1/4 full scale bias current
1/2 full scale bias current
Full scale bias current
x
x
x
0
0
1
1
0
1
0
1
No offset
1/4 of full scale bias current offset
1/2 of full scale bias current offset
3/4 of full scale bias current offset
x
x
2053 Reg0 1.0
Register 0
2053 2.2 11/07/00
SUMMIT MICROELECTRONICS, Inc.
11
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
