SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
Configuration
Register Address
R
O
Master
Bus Address
Data
T
P
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
W
Slave
A
C
K
A
C
K
A
C
K
Figure 12 – Register Byte Write
S
T
A
R
T
Configuration
Register Address
Master
Bus Address
Data (1)
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
W
Slave
A
C
K
A
C
K
A
C
K
S
T
O
P
Master
Slave
Data (2)
Data (16)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
A
C
K
Figure 13 – Register Page Write
S
S
T
A
R
T
T
A
R
T
Configuration
Master
Bus Address
Bus Address
Register Address
S
S
S
A
1
S
A
0
S
S
S
S
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
W
R
A
3
A
2
A
3
A
2
A
1
A
0
Slave
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
D
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
D
4
D
3
D
D
1
D
0
6
5
5
2
A
C
K
A
C
K
Figure 14 – Register Read
Summit Microelectronics, Inc
2111 2.4 6/24/2008
30