SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The input capacitance must be chosen such that the
rise and fall times specified in the datasheet do not
exceed ~5% of the switching period.
Equations 4, 5:
VO
VIN
Buck − NFET : (1−
)*T
To ensure the maximum load current will not exceed
the power rating of the FET, the power dissipation of
each FET must be determined. It is important to look
at each FET individually and then add the power
dissipation of complementary FETs after the power
dissipation over one cycle has been determined. The
Power dissipation can be approximated as follows:
VO
Buck − PFET :
VIN
*T
Compensation:
2
Summit provides a design tool to called Summit Power
Designer” that will automatically calculate the
compensation values for a design or allow the system
to be customized for a particular application. The
power designer software can be found at
http://www.summitmicro.com/prod_select/xls/SummitP
owerDesigner_Install.zip.
P ~ RDSON * IL *TON
Equation 3:
Where TON is the on time of the primary switch. TON
can be calculated as follows:
Summit Microelectronics, Inc
2111 2.4 6/24/2008
26
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
