USBLC6-2
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the
PSPICE parameters given in figure 17.
Figure 16: PSPICE model
LI/O
D+in
RI/O
MODEL = Dlow
MODEL = Dhigh
RI/O
LI/O
D+out
LGND
GND
RGND
MODEL = Dzener
RI/O
LI/O
VBUS
MODEL = Dlow
LI/O
D-in
RI/O
MODEL = Dhigh
RI/O
LI/O
D-out
Note:
This simulation model is available only for an ambient temperature of 27°C.
Figure 17: PSPICE parameters
Figure
18:
considerations
USBLC6-2
PCB
layout
Dlow
BV
CJ0
IBV
M
RS
VJ
TT
50
0.9p
1m
0.3333
0.2
0.6
0.1u
Dhigh
50
2.0p
1m
0.3333
0.52
0.6
0.1u
Dzener
7.3
40p
1m
0.3333
0.84
0.6
0.1u
LI/O
RI/O
LGND
RGND
750p
110m
550p
60m
D+in
1
D+out
V
BUS
GND
D-in
C
BUS
= 100nF
USBLC6-2
D-out
8/11
STMICROELECTRONICS [ STMICROELECTRONICS ]
