TDA7719
Description
4
Description
4.1
Input stages
nd
The input stage (Main source and 2 source) is configurable to adapt to different
application. There are 7 different configurations which provide different input structure and
different number of input sources as shown below.
●
●
●
●
●
●
●
●
4 x QD,
2 x QD + 3 x SE,
1 x QD + 5 x SE,
1 x QD + 3 x SE + 2 x MD,
3 x QD + 1 x FD,
3 x QD + 2 x SE,
1 x QD + 2 x SE + 1 x FD + 1 x MD,
1 x QD + 3 x SE + 1 x FD
Note:
QD = Quasi-Differential, SE = Single-ended input, FD = Full Differential, MD = mono
Differential
2
The configuration of the input stage is controlled by ‘Input Configuration’ bits in I C control
table (Byte0 Bit5~Bit7). The table blow shows the configuration of input pins in different
configurations.
Table 6.
Input pin configuration
Configuration bits (Byte0 Bit7~Bit5)
Pin Pin name
"000"
"001"
"010"
"011"
"100"
"101"
"110"
"111"
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
QD1L_SE1L
_MD3+
QD1L
SE1L
SE1L
SE1L
QD1L
QD1L
MD3+
SE1L
1
IN0
IN0
IN0
IN7
IN0
QD1R_SE1R
_MD3-
IN0
IN0
IN0
QD1R
SE1R
SE1R
SE1R
QD1R
QD1R
MD3-
SE1R
2
QD1G_SE2L
QD1G
QD2G
SE2L
SE2R
SE3L
SE3R
QD3L
SE2L
SE2R
SE3L
SE3R
QD3L
SE2L
SE2R
SE3L
SE3R
QD3L
QD1G
QD2G
QD1G
QD2G
SE2L
SE2R
SE2L
SE2R
SE3L
SE3R
QD3L
3
IN4
IN1
IN4
IN1
IN4
IN1
IN4
IN1
IN4
IN1
QD2G_SE2R
4
QD2L_SE3L
QD2L IN1
QD2R
QD2L IN1 QD2L IN1 SE3L
5
QD2R_SE3R
QD2R
QD3L
QD2R
QD3L
SE3R
QD3L
6
QD3L
QD3L
7
QD3G
QD3G IN2 QD3G IN2 QD3G IN2 QD3G IN2 QD3G IN2 QD3G IN2 QD3G IN2 QD3G IN2
8
QD3R
QD3R
QD4L
QD3R
QD4L
QD3R
SE4L
QD3R
MD1+
QD3R
FD4L+
QD3R
SE4L
QD3R
FD4L+
QD3R
9
QD4L_FD4+
10
FD4L+ IN3
_SE4L_MD1+
IN5
IN6
IN3
IN3
IN5
IN6
QD4G_FD4L
11
QD4G
QD4G
QD4R
QD4G
QD4G
QD4R
SE4R
SE5L
SE5R
MD1-
MD2-
MD2+
FD4L-
FD4R-
SE4R
SE5L
SE5R
FD4L-
FD4R-
FD4R+
FD4L-
FD4R-
FD4R+
_SE4R_MD1-
IN3
IN3
IN3
IN3
QD4G_FD4R_S
12
E5L_MD2-
QD4R_FD4R+_
13
FD4R
+
SE5R_MD2+
13/45
STMICROELECTRONICS [ ST ]
