Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 48. I
2
S slave timing diagram (Philips protocol)
(1)
tc(CK)
CK Input
CPOL = 0
CPOL = 1
tw(CKH)
WS input
t
su(WS)
SD
transmit
LSB transmit
(2)
t
su(SD_SR)
SD
receive
LSB receive
(2)
MSB receive
MSB transmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
LSB receive
th(SD_ST)
LSB transmit
tw(CKL)
th(WS)
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × V
DD
and 0.7 × V
DD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 49. I
2
S master timing diagram (Philips protocol)
(1)
tf(CK)
tr(CK)
tc(CK)
CK output
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
WS output
tv(SD_MT)
SD
transmit
LSB transmit
(2)
t
su(SD_MR)
SD
receive
LSB receive
(2)
MSB receive
MSB transmit
Bitn transmit
th(SD_MR)
Bitn receive
LSB receive
th(SD_MT)
LSB transmit
tw(CKL)
th(WS)
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
94/123
Doc ID 14611 Rev 7
STMICROELECTRONICS [ STMICROELECTRONICS ]
