Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
I
2
S - SPI characteristics
Unless otherwise specified, the parameters given in
for SPI or in
for I
2
S
are derived from tests performed under ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions summarized in
Refer to
for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
2
S).
Table 52.
Symbol
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
DuCy(SCK)
t
su(NSS)(2)
t
h(NSS)(2)
t
w(SCKH)(2)
t
w(SCKL)(2)
t
su(MI) (2)
t
su(SI)(2)
t
h(MI) (2)
t
h(SI)(2)
t
a(SO)(2)(3)
t
dis(SO)(2)(4)
t
v(SO) (2)(1)
t
v(MO)(2)(1)
t
h(SO)(2)
t
h(MO)(2)
SPI characteristics
(1)
Parameter
SPI clock frequency
Slave mode
SPI clock rise and fall
time
Capacitive load: C = 30 pF
30
4t
PCLK
2t
PCLK
50
5
5
5
4
0
2
3t
PCLK
10
25
5
15
2
ns
60
18
8
70
ns
%
Conditions
Master mode
Min
Max
18
MHz
Unit
SPI slave input clock duty
Slave mode
cycle
NSS setup time
NSS hold time
SCK high and low time
Slave mode
Slave mode
Master mode, f
PCLK
= 36 MHz,
presc = 4
Master mode
Data input setup time
Slave mode
Master mode
Data input hold time
Slave mode
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Master mode (after enable edge)
Slave mode, f
PCLK
= 20 MHz
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Doc ID 14611 Rev 7
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