STM32F103xC, STM32F103xD, STM32F103xE
Table 53.
Symbol
DuCy(SCK)
Electrical characteristics
I
2
S characteristics
Parameter
I2S slave input clock duty
cycle
I
2
S clock frequency
Conditions
Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
Slave mode
I
2
S clock rise and fall time
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Capacitive load C
L
= 50 pF
Master mode
I2S2
Master mode
I2S3
Slave mode
Slave mode
Master f
PCLK
= 16 MHz, audio
frequency = 48 kHz
I2S2
Data input setup time
Data input setup time
Data input hold time
Slave receiver
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
0
11
3
0.5
18
Master receiver
I2S3
Slave receiver
Master receiver
6.5
1.5
0
0
4
0
312.5
345
2
3
2
Min
30
1.522
0
Max
70
1.525
MHz
6.5
8
ns
Unit
%
f
CK
1/t
c(CK)
t
r(CK)
t
f(CK)
t
v(WS) (1)
t
h(WS) (1)
t
su(WS) (1)
t
h(WS) (1)
t
w(CKH) (1)
t
w(CKL) (1)
t
su(SD_MR) (1)
t
su(SD_SR) (1)
t
h(SD_MR)(1)(2)
t
h(SD_SR) (1)(2)
t
v(SD_ST) (1)(2)
t
h(SD_ST) (1)
t
v(SD_MT) (1)(2)
t
h(SD_MT) (1)
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f
PCLK
. For example, if f
PCLK
=8 MHz, then T
PCLK
= 1/f
PLCLK
=125 ns.
Doc ID 14611 Rev 7
93/123
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