Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
Conditions
T
A
�½+105
°C conforming to JESD78A
Class
II level A
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
are derived from tests
performed under the conditions summarized in
All I/Os are CMOS and TTL
compliant.
Table 45.
Symbol
V
IL
V
IH
V
IL
V
IH
I/O static characteristics
Parameter
Input low level voltage
Standard IO input high level voltage
IO FT
(1)
input high level voltage
Input low level voltage
CMOS ports
Input high level voltage
Standard IO Schmitt trigger voltage
hysteresis
(2)
0.65 V
DD
200
5% V
DD(3)
V
SS
V
IN
V
DD
Standard I/Os
V
IN
= 5 V,
I/O FT
1
µA
3
30
30
40
40
5
50
50
k
k
pF
TTL ports
Conditions
Min
–0.5
2
2
–0.5
Typ
Max
0.8
V
V
DD
+0.5
5.5V
0.35 V
DD
V
DD
+0.5
mV
mV
V
Unit
V
hys
IO FT Schmitt trigger voltage
hysteresis
(2)
Input leakage current
(4)
Weak pull-up equivalent resistor
(5)
Weak pull-down equivalent resistor
(5)
I/O pin capacitance
I
lkg
R
PU
R
PD
C
IO
V
IN
�½
V
SS
V
IN
�½
V
DD
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum
(~10% order)
.
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Doc ID 14611 Rev 7
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