STM32F103xC, STM32F103xD, STM32F103xE
Table 39.
Symbol
t
w(NIOWR)
t
v(NIOWR-D)
t
h(NIOWR-D)
Electrical characteristics
Switching characteristics for PC Card/CF read and write cycles
(1)(2)
(continued)
Parameter
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
11T
HCLK
5T
HCLK
+3ns
5T
HCLK
– 5
5T
HCLK
+ 2.5
5T
HCLK
– 5
4.5
9
8T
HCLK
+ 2
Min
8T
HCLK
+ 3
5T
HCLK
+1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d(NCE4_1-NIOWR)
FSMC_NCE4_1 low to FSMC_NIOWR valid
t
h(NCEx-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
t
h(NCE4_1-NIOWR)
FSMC_NCE4_1 high to FSMC_NIOWR invalid
t
d(NIORD-NCEx)
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
t
d(NIORD-NCE4_1)
low to FSMC_NIORD valid
t
h(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD invalid
t
h(NCE4_1-NIORD)
FSMC_NCE4_1 high to FSMC_NIORD invalid
t
su(D-NIORD)
t
d(NIORD-D)
t
w(NIORD)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
FSMC_NIORD low width
NAND controller waveforms and timings
through
represent synchronous waveforms and
provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
Doc ID 14611 Rev 7
77/123
STMICROELECTRONICS [ STMICROELECTRONICS ]
