STM32F103x8, STM32F103xB
Table 59. Document revision history (continued)
Revision history
Date
Revision
Changes
I/O information clarified on page 1.
Figure 3: STM32F103xx performance line LFBGA100 ballout modified.
Figure 10: Memory map modified. Table 4: Timer feature comparison
added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column in Table 5: Medium-density STM32F103xx
pin definitions.
PD for LFBGA100 corrected in Table 9: General operating conditions.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
23-Apr-2009
10
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
Figure 19 shows a typical curve (title modified). ACCHSI max values
modified in Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Table 55 and Table 50). Small text
changes.
Note 5 updated and Note 4 added in Table 5: Medium-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 12: Embedded internal reference
voltage. IDD_VBAT value added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes. Figure 17: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE
=
32.768 kHz), notes modified and moved below the tables. Table 24: HSI
oscillator characteristics modified. Conditions removed from Table 26:
Low-power mode wakeup timings.
22-Sep-2009
11
Note 1 modified below Figure 23: Typical application with an 8 MHz
crystal.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 55.
Jitter added to Table 27: PLL characteristics.
Table 41: SPI characteristics modified.
CADC and RAIN parameters modified in Table 45: ADC characteristics.
RAIN max values modified in Table 46: RAIN max for fADC = 14 MHz.
Figure 44: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline updated.
Added STM32F103TB devices.
Added VFQFPN48 package.
Updated note 2 below Table 39: I2C characteristics
Updated Figure 31: I2C bus AC waveforms and measurement circuit
Updated Figure 30: Recommended NRST pin protection
Updated Section 5.3.12: I/O port characteristics
03-Jun-2010
12
Doc ID 13587 Rev 12
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