STM32F103x8, STM32F103xB
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 9. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
VOL
0.4
TTL port
IIO = +8 mA
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
2.7 V < VDD < 3.6 V
VOH
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
VOL
0.4
1.3
0.4
CMOS port
IIO =+ 8mA
V
V
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
2.7 V < VDD < 3.6 V
VOH
2.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(3)
VOL
I
IO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(3)
VOH
VDD–1.3
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(3)
VOL
IIO = +6 mA
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(3)
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. Based on characterization data, not tested in production.
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