Electrical characteristics
STM32F103x8, STM32F103xB
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard I/O input low level
voltage
–0.5
–0.5
0.28 (VDD–2)+0.8
0.32 (VDD–2)+0.75
VDD+0.5
VIL
I/O FT(1) input low level voltage
V
Standard I/O input high level
voltage
0.41 (VDD–2)+1.3
0.42 (VDD–2)+1
200
VIH
I/O FT(1) input high level voltage
5.5
Standard IO Schmitt trigger
voltage hysteresis(2)
mV
mV
Vhys
IO FT Schmitt trigger voltage
hysteresis(2)
(3)
5% VDD
VSS VIN VDD
Standard I/Os
1
3
Ilkg
Input leakage current (4)
µA
VIN= 5 V
I/O FT
Weak pull-up equivalent
resistor(5)
RPU
VIN VSS
VIN VDD
30
30
40
50
50
k
Weak pull-down equivalent
resistor(5)
RPD
CIO
40
5
k
I/O pin capacitance
pF
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 25 and Figure 26 for standard I/Os, and
in Figure 27 and Figure 28 for 5 V tolerant I/Os.
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