STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
2
Table 38. I C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
1.3
0.6
100
0(4)
µs
250
0(3)
th(SDA)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
300
th(STA)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated Start condition setup
time
tsu(STA)
tsu(STO) Stop condition setup time
µs
µs
pF
Stop to Start condition time (bus
tw(STO:STA)
free)
Cb
Capacitive load for each bus line
400
400
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than
4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
maximum I2C fast mode clock.
The maximum hold time of the Start condition only has to be met if the interface does not stretch the low
period of SCL signal.
3.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4.
Doc ID 16455 Rev 2
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STMICROELECTRONICS [ ST ]
