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STM32F405RG 参数 Datasheet PDF下载

STM32F405RG图片预览
型号: STM32F405RG
PDF下载: 下载PDF文件 查看货源
内容描述: ARM的Cortex- M4 32B MCUFPU , 210DMIPS ,高达1MB闪存/ 1924KB RAM , USB OTG HS / FS [ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS]
分类和应用: 闪存
文件页数/大小: 185 页 / 5432 K
品牌: STMICROELECTRONICS [ ST ]
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Description  
STM32F405xx, STM32F407xx  
Table 5. USART feature comparison  
Max. baud rate Max. baud rate  
Modem  
(RTS/ LIN  
CTS)  
USART Standard  
SPI  
master  
Smartcard  
in Mbit/s in Mbit/s  
APB  
irDA  
name  
features  
(ISO 7816) (oversampling (oversampling mapping  
by 16)  
by 8)  
APB2  
(max.  
84 MHz)  
USART1  
USART2  
USART3  
UART4  
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
-
5.25  
10.5  
APB1  
(max.  
42 MHz)  
2.62  
2.62  
2.62  
2.62  
5.25  
5.25  
5.25  
5.25  
5.25  
10.5  
APB1  
(max.  
42 MHz)  
APB1  
(max.  
42 MHz)  
APB1  
(max.  
42 MHz)  
UART5  
-
-
-
APB2  
(max.  
USART6  
X
X
X
84 MHz)  
2.2.24  
Serial peripheral interface (SPI)  
The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and  
simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3  
can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies  
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification  
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.  
The SPI interface can be configured to operate in TI mode for communications in master  
mode and slave mode.  
2
2.2.25  
Inter-integrated sound (I S)  
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available. They can be  
operated in master or slave mode, in full duplex and half-duplex communication modes, and  
can be configured to operate with a 16-/32-bit resolution as an input or output channel.  
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of  
2
the I S interfaces is/are configured in master mode, the master clock can be output to the  
external DAC/CODEC at 256 times the sampling frequency.  
2
All I Sx can be served by the DMA controller.  
2.2.26  
Audio PLL (PLLI2S)  
2
The devices feature an additional dedicated PLL for audio I S application. It allows to  
2
achieve error-free I S sampling clock accuracy without compromising on the CPU  
performance, while using USB peripherals.  
34/185  
DocID022152 Rev 4  
 
 
 
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