STM32F105xx, STM32F107xx
Electrical characteristics
2
(1)
Figure 28. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 29. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Doc ID 15274 Rev 6
69/104
STMICROELECTRONICS [ ST ]
