Electrical characteristics
STM32F105xx, STM32F107xx
2
Table 44. I S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master data: 16 bits, audio
freq = 48 K
1.52
0
1.54
6.5
8
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave
tr(CK)
tf(CK)
I2S clock rise and fall time
capacitive load CL = 50 pF
(1)
tw(CKH)
I2S clock high time
I2S clock low time
WS valid time
317
333
3
320
336
Master fPCLK = 16 MHz,
audio freq = 48 K
(1)
tw(CKL)
(1)
tv(WS)
Master mode
ns
I2S2
Master mode
0
(1)
th(WS)
WS hold time
I2S3
0
I2S2
Slave mode
4
(1)
tsu(WS)
WS setup time
WS hold time
I2S3
9
(1)
th(WS)
Slave mode
Slave mode
0
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
I2S2
Master receiver
I2S3
8
10
3
(1)
tsu(SD_MR)
Data input setup time
Data input hold time
I2S2
Slave receiver
I2S3
(1)
tsu(SD_SR)
8
I2S2
Master receiver
I2S3
2
(1)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
4
I2S2
Slave receiver
I2S3
2
(1)
4
ns
I2S2
23
33
29
27
Slave transmitter
(1)(3)
(1)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
(after enable edge)
I2S3
I2S2
Slave transmitter
(after enable edge)
I2S3
I2S2
5
2
Master transmitter
(1)
(after enable edge)
I2S3
I2S2
11
4
Master transmitter
(1)
(after enable edge)
I2S3
1. Based on design simulation and/or characterization results, not tested in production.
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Doc ID 15274 Rev 6
STMICROELECTRONICS [ ST ]
