STM32F105xx, STM32F107xx
Electrical characteristics
I2S - SPI interface characteristics
2
Unless otherwise specified, the parameters given in Table 43 for SPI or in Table 44 for I S
are derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 9.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK,
2
SD for I S).
Table 43. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
%
SPI slave input clock
duty cycle
DuCy(SCK)
Slave mode
30
70
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 tPCLK
2 tPCLK
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
50
60
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Master mode
Slave mode
Master mode
Slave mode
4
5
5
5
Data input hold time
ns
Data output access
time
ta(SO)
Slave mode, fPCLK = 20 MHz
3*tPCLK
tv(SO)
tv(MO)
th(SO)
th(MO)
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
34
8
Slave mode (after enable edge)
Data output hold time
32
10
Master mode (after enable edge)
Doc ID 15274 Rev 6
65/104
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