Electrical characteristics
Figure 23. Recommended NRST pin protection
STM32F105xx, STM32F107xx
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal reset
NRST
Filter
0.1 µF
STM32F10x
ai14132d
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 39. Otherwise the reset will not be taken into account by the device.
5.3.15
TIM timer characteristics
The parameters given in Table 40 are guaranteed by design.
Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
(1)
Table 40. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 72 MHz
TIMxCLK = 72 MHz
13.9
0
ns
MHz
MHz
bit
fTIMxCLK/2
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
36
16
ResTIM
Timer resolution
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
910
tCOUNTER
fTIMxCLK = 72 MHz
fTIMxCLK = 72 MHz
0.0139
µs
tTIMxCLK
s
65536 × 65536
59.6
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers.
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