Electrical characteristics
STM32F103x8, STM32F103xB
5.3.16
Communications interfaces
I
2
C interface characteristics
The STM32F103xx performance line I
2
C interface meets the requirements of the standard
I
2
C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in
Refer also to
for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 40.
Symbol
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
t
su(STO)
t
w(STO:STA)
C
b
I
2
C characteristics
Standard mode I
2
C
(1)
Parameter
Min
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
4.0
4.7
4.0
4.7
400
4.7
4.0
250
0
1000
300
0.6
µs
0.6
0.6
1.3
400
μs
μs
pF
Max
Min
1.3
µs
0.6
100
0
20 + 0.1C
b
900
(3)
300
300
ns
Max
Fast mode I
2
C
(1)(2)
Unit
1. Guaranteed by design, not tested in production.
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve fast mode I
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
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Doc ID 13587 Rev 15
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