Electrical characteristics
STM32F103x8, STM32F103xB
SPI interface characteristics
Unless otherwise specified, the parameters given in
are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage
conditions summarized in
Refer to
for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 42.
Symbol
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
DuCy(SCK)
SPI characteristics
Parameter
SPI clock frequency
Slave mode
SPI clock rise and fall
time
SPI slave input clock
duty cycle
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
30
4t
PCLK
2t
PCLK
50
5
5
5
4
0
2
3t
PCLK
10
25
5
15
2
ns
60
18
8
70
ns
%
Conditions
Master mode
Min
Max
18
MHz
Unit
t
su(NSS)(1)
NSS setup time
t
h(NSS)(1)
NSS hold time
Master mode, f
PCLK
= 36 MHz,
t
w(SCKH)(1)
SCK high and low time
t
w(SCKL)(1)
presc = 4
t
su(MI) (1)
t
su(SI)(1)
t
h(MI) (1)
t
h(SI)(1)
t
a(SO)(1)(2)
t
dis(SO)(1)(3)
t
v(SO) (1)
t
v(MO)(1)
t
h(SO)(1)
t
h(MO)(1)
Master mode
Data input setup time
Slave mode
Master mode
Data input hold time
Slave mode
Data output access
time
Data output disable
time
Data output valid time
Data output valid time
Data output hold time
Master mode (after enable edge)
Slave mode, f
PCLK
= 20 MHz
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Doc ID 13587 Rev 15
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