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STM32F103C8T7 参数 Datasheet PDF下载

STM32F103C8T7图片预览
型号: STM32F103C8T7
PDF下载: 下载PDF文件 查看货源
内容描述: 中密度高性能线的基于ARM的32位MCU,具有64或128 KB的闪存, USB , CAN ,7个定时器, 2的ADC , 9融为一体。接口 [Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces]
分类和应用: 闪存
文件页数/大小: 105 页 / 1316 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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Electrical characteristics
STM32F103x8, STM32F103xB
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V
OL
/V
OH
) except PC13, PC14 and PC15 which can
sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in
The sum of the currents sourced by all the I/Os on V
DD,
plus the maximum Run
consumption of the MCU sourced on V
DD,
cannot exceed the absolute maximum rating
I
VDD
(see
The sum of the currents sunk by all the I/Os on V
SS
plus the maximum Run
consumption of the MCU sunk on V
SS
cannot exceed the absolute maximum rating
I
VSS
(see
Output voltage levels
Unless otherwise specified, the parameters given in
are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
All I/Os are CMOS and TTL compliant.
Table 36.
Symbol
V
OL(1)
V
OH(3)
V
OL (1)
V
OH (3)
V
OL(1)(4)
V
OH(3)(4)
V
OL(1)(4)
V
OH(3)(4)
Output voltage characteristics
Parameter
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Conditions
CMOS port
(2)
,
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
TTL port
(2)
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
Min
Max
0.4
V
V
DD
–0.4
0.4
V
2.4
1.3
V
V
DD
–1.3
0.4
V
V
DD
–0.4
Unit
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
4. Based on characterization data, not tested in production.
66/105
Doc ID 13587 Rev 15