Electrical characteristics
STM32F103x8, STM32F103xB
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 35. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO
input low level
voltage
-
-
0.28*(VDD-2 V)+0.8 V(1)
VIL
Low level input voltage IO FT(3) input
low level voltage
-
-
-
-
0.32*(VDD-2V)+0.75 V(1)
All I/Os except
BOOT0
(2)
0.35VDD
V
Standard IO
input high level 0.41*(VDD-2 V)+1.3 V(1)
voltage
-
-
IO FT(3) input
high level
voltage
VIH
High level input voltage
0.42*(VDD-2 V)+1 V(1)
-
-
-
-
-
-
All I/Os except
BOOT0
(2)
0.65VDD
Standard IO Schmitt
trigger voltage
hysteresis(4)
200
Vhys
mV
µA
IO FT Schmitt trigger
voltage hysteresis(4)
(5)
5% VDD
-
-
-
1
VSS ≤ VIN ≤ VDD
Standard I/Os
-
-
Input leakage current
Ilkg
(6)
VIN = 5 V
I/O FT
-
3
Weak pull-up
RPU
VIN = VSS
VIN = VDD
30
40
50
equivalent resistor(7)
kΩ
Weak pull-down
RPD
CIO
30
-
40
5
50
-
equivalent resistor(7)
I/O pin capacitance
pF
1. Data based on design simulation.
2. Tested in production.
3. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage could be higher than max. if negative current is injected on adjacent pins.
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