STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.18
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 57. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
VREF+
fADC
ADC power supply
2.4
2.4
0.6
3.6
VDDA
14
V
V
Positive reference voltage
ADC clock frequency
MHz
(1)
Sampling rate
0.05
1
MHz
fS
823
17
kHz
(1)
External trigger frequency
fADC = 14 MHz
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
Conversion voltage range(2)
VREF+
V
VAIN
(1)
RAIN
External input impedance
Sampling switch resistance
See Equation 1 and Table 58
kΩ
kΩ
(1)
1
RADC
Internal sample and hold
capacitor
(1)
5
pF
CADC
5.9
83
µs
1/fADC
µs
(1)
Calibration time
fADC = 14 MHz
fADC = 14 MHz
tCAL
0.214
Injection trigger conversion
latency
(1)
tlat
3(3)
0.143
2(3)
1/fADC
µs
Regular trigger conversion
latency
(1)
f
ADC = 14 MHz
tlatr
1/fADC
µs
0.107
1.5
0
17.1
239.5
1
(1)
Sampling time
Power-up time
fADC = 14 MHz
tS
1/fADC
µs
(1)
tSTAB
0
1
18
µs
Total conversion time
(including sampling time)
(1)
fADC = 14 MHz
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Guaranteed by design, not tested in production.
2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 57.
99/118
STMICROELECTRONICS [ ST ]
