STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
(1)
Table 39. Switching characteristics for NAND Flash read and write cycles
Timing
Symbol
Parameter
Unit
Min
Max
tv(NCEx-A)
th(NCEx-AI)
FSMC_NCEx low (x = 2/3) to FSMC_Ay valid (y = 16/17)
-
TBD
ns
ns
FSMC_NCEx high (x = 2/3) to FSMC_Ax invalid (x =
16/17)
TBD
-
td(D-NWE)
td(NWE-D)
td(NCEx-NOE)
tw(NOE)
FSMC_D[15:0] valid before FSMC_NWE high
FSMC_D[15:0] valid after FSMC_NWE high
FSMC_NCEx low to FSMC_NOE low
FSMC_NOE low width
TBD
TBD
-
-
-
ns
ns
ns
TBD
TBD
TBD cycles/ns
th(NWE-D)
FSMC_NWE high to FSMC_D[15:0] invalid
ns
td(NOE-NWAITL) FSMC_NWAIT low after FSMC_NOE low(2)
td(NOE-NWAITH) FSMC_NWAIT high after FSMC_NOE low(2)
TBD
TBD
TBD
TBD
TBD
-
td(NWAIT-NOE)
tsu(D-NOE)
FSMC_NOE high after FSMC_NWAIT high
FSMC_D[15:0] valid data before FSMC_NOE high
FSMC_D[15:0] valid data after FSMC_NOE high
FSMC_NCEx low to FSMC_NWE low
FSMC_NWE low width
-
ns
ns
ns
ns
-
-
th(NOE-D)
td(NCEx-NWE)
tw(NWE)
TBD
TBD
TBD
TBD cycles/ns
ns
td(NWE-NCEx)
FSMC_NWE high to FSMC_NCEx high
td(NWE-NWAITL) FSMC_NWAIT low after FSMC_NWE low(2)
td(NWE-NWAITH) FSMC_NWAIT high after FSMC_NWE low(2)
td(NWAIT-NWE) FSMC_NWE high after FSMC_NWAIT high
TBD
ns
ns
ns
ns
ns
TBD
TBD
-
-
TBD
-
tv(NWE-D)
th(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
FSMC_NWE high to FSMC_D[15:0] invalid
TBD
1. TBD = to be determined.
2. When one or more wait states are inserted. If no wait state needs inserted, NWAIT should be kept high or
the wait feature should be disabled (WAITEN=0) in the control register.
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STMICROELECTRONICS [ ST ]
