STM32F103xC, STM32F103xD, STM32F103xE
Electromagnetic Interference (EMI)
Electrical characteristics
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
(1)
Table 41. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz 8/72 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
VDD = 3.3 V, TA = 25 °C,
LQFP100 package
compliant with SAE J
1752/3
dBµV
-
SEMI
Peak level
1. TBD = to be determined.
5.3.12
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 42. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
TA = +25 °C
conforming to
JESD22-A114
Electrostatic discharge
voltage (human body model)
VESD(HBM)
2
2000
500
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C
conforming to
JESD22-C101
II
1. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
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STMICROELECTRONICS [ ST ]
