Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.19
Table 61.
Symbol
V
DD33A
V
DD18D
V
REF+
V
SSA
R
L
C
L
DAC electrical specifications
DAC characteristics
Parameter
Analog supply voltage
Digital supply voltage
Reference supply voltage
Ground
Resistive load with buffer ON
Capacitive load
0.2
Min
2.4
1.6
2.4
0
5
50
1.8
Typ
Max
(1)
3.6
2
3.6
0
Unit
V
V
V
V
kΩ
pF
V
Minimum resistive load between
DAC_OUT and V
SSA
Maximum capacitive load at
DAC_OUT pin.
It gives the maximum output
excursion of the DAC
it corresponds to 12-bit input
code (0E0)h to (F1C)h @ V
REF+
= 3.6 V and (155)h and (EAB)h
@ V
REF+
= 2.4 V
With no load, middle code
(800)H on the inputs
With no load, worst code
(F1C)H @ V
REF+
= 3.6 V in
terms of DC consumption on the
inputs
V
REF+
must always be below
V
DD33A
Comments
DAC_OUT Lower DAC_OUT voltage with
min
buffer ON
DAC_OUT Higher DAC_OUT voltage with
max
buffer ON
V
REF+
– 0.2 V
V
425
I
DD
DAC DC current consumption
in quiescent mode (Standby
mode) (in V
DD18D
+V
DD33A
+
V
REF+
)
DAC DC current consumption
in Power Down mode (in
V
DD18D
+V
DD33A
+V
REF+
)
DAC DC current consumption
in Power Down mode (in
V
DD33A
+V
REF+
)
Differential non linearity
(Difference between two
consecutive code-1LSB)
Integral non linearity (difference
between measured value at
Code i and the value at Code i
on a line drawn between Code
0 and last Code 1023)
Offset error
(difference between measured
value at Code (800)H and the
ideal value = V
REF+
/2
Gain error
600
µA
500
700
µA
5
350
nA
With no load.
I
DDQ
5
200
DNL
±0.5
LSB
Given for the DAC in 10-bit
configuration (B1=B0=0 always)
INL
±1
LSB
Given for the DAC in 10-bit
configuration (B1=B0=0 always)
±10
±3
±0.5
mV
LSB
%
Given for the DAC in 10-bit
configuration (B1=B0=0 always)
Given for the DAC in 10-bit @
V
REF+
= 3.6 V
Given for the DAC in 10-bit
configuration (B1=B0=0 always)
Offset
Gain error
104/118
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