Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 52. Typical connection diagram using the ADC
V
DD
STM32F103xx
V
0.6 V
T
(1)
AIN
(1)
ADC
R
R
I
AINx
12-bit A/D
conversion
(1)
C
ADC
V
T
1 µA
V
C
L
AIN
0.6 V
AIN
ai14150b
1. Refer to Table 57 for the values of CAIN, RAIN, RADC and CADC
.
2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 53 or Figure 54,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 53. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F103xx
V
REF+
(see note 1)
1 µF // 10 nF
V
DDA
SSA
1 µF // 10 nF
V
/V
REF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
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