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STM32F103R8T6 参数 Datasheet PDF下载

STM32F103R8T6图片预览
型号: STM32F103R8T6
PDF下载: 下载PDF文件 查看货源
内容描述: 性能线,基于ARM的32位MCU和Flash , USB , CAN , 7个16位定时器,2个ADC和9通信接口 [Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces]
分类和应用: 微控制器和处理器外围集成电路PC通信时钟
文件页数/大小: 67 页 / 1083 K
品牌: STMICROELECTRONICS [ ST ]
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Electrical characteristics  
STM32F103xx  
Input/output AC characteristics  
The definition and values of input/output AC characteristics are given in Figure 16 and  
Table 31, respectively.  
Unless otherwise specified, the parameters given in Table 31 are derived from tests  
performed under ambient temperature and V supply voltage conditions summarized in  
DD  
Table 7.  
(1)  
Table 31. I/O AC characteristics  
I/O  
Symbol  
Parameter  
Conditions  
Min Max Unit  
mode(1)  
fmax(IO)out Maximum frequency(2)  
CL = 50 pF, VDD = 2 V to 3.6 V  
2
MHz  
ns  
Output high to low level fall  
tf(IO)out  
125  
10  
time(3)  
CL = 50 pF, VDD = 2 V to 3.6 V  
CL = 50 pF, VDD = 2 V to 3.6 V  
CL = 50 pF, VDD = 2 V to 3.6 V  
Output low to high level  
tr(IO)out  
125  
rise time(3)  
fmax(IO)out Maximum frequency(2)  
10 MHz  
Output high to low level fall  
tf(IO)out  
25  
ns  
25  
01  
time(3)  
Output low to high level  
tr(IO)out  
rise time(3)  
CL = 30 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2 V to 2.7 V  
CL = 30 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2 V to 2.7 V  
CL = 30 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2.7 V to 3.6 V  
CL = 50 pF, VDD = 2 V to 2.7 V  
50 MHz  
Fmax(IO)out Maximum frequency(2)  
30 MHz  
20 MHz  
5
8
Output high to low level fall  
11  
tf(IO)out  
time(3)  
12  
ns  
5
Output low to high level  
tr(IO)out  
8
rise time(3)  
12  
Pulse width of external  
tEXTIpw signals detected by the  
EXTI controller  
-
10  
ns  
1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register.  
2. The maximum frequency is defined in Figure 16.  
3. Values based on design simulation and validated on silicon, not tested in production.  
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