STM32F103xx
Electrical characteristics
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 7.
2
I
The STM32F103xx performance line C interface meets the requirements of the standard
2
I C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V is disabled, but is still present. In addition, there is a protection
DD
diode between the I/O pin and V . As a consequence, when multiple master devices are
DD
2
2
I C
I
connected to the
bus, it is not possible to power off the STM32F103xx while another
C
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
2
The I C characteristics are described in Table 34. Refer also to Section 5.3.12: I/O port pin
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
Table 34. I C characteristics
Standard mode I2C(1)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
µs
250
0(3)
100
0(4)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
20 + 0.1Cb
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
20 + 0.1Cb
300
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
µs
µs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
400
400
pF
Values based on standard I2C protocol requirement, not tested in production.
1.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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