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STM32F103R8T6 参数 Datasheet PDF下载

STM32F103R8T6图片预览
型号: STM32F103R8T6
PDF下载: 下载PDF文件 查看货源
内容描述: 性能线,基于ARM的32位MCU和Flash , USB , CAN , 7个16位定时器,2个ADC和9通信接口 [Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces]
分类和应用: 微控制器和处理器外围集成电路PC通信时钟
文件页数/大小: 67 页 / 1083 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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Electrical characteristics
STM32F103xx
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size is
either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).
The human body model (HBM) can be simulated. The tests are compliant with JESD22-
A114A standard.
For more details, refer to the application note AN1181.
Table 27.
Symbol
V
ESD(HBM)
V
ESD(CDM)
ESD absolute maximum ratings
(1)
Ratings
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
Conditions
Maximum value
(2)
2000
T
A
=
+25 °C
TBD
V
Unit
1. TBD stands for to be determined.
2. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 28.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
T
A
=
+105 °C
Conditions
Class
II level A
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