STA335BW
Register description
Table 29. RAM block for biquads, mixing, scaling and bass management (continued)
Index (Decimal)
Index (Hex)
Coefficient
Default
54
55
56
57
58
59
60
61
62
63
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Channel 3 – Post-Scale
TWARN/OC– Limit
Channel 1 – Mix 1
Channel 1 – Mix 2
Channel 2 – Mix 1
Channel 2 – Mix 2
Channel 3 – Mix 1
Channel 3 – Mix 2
UNUSED
C3PstS
TWOCL
C1MX1
C1MX2
C2MX1
C2MX2
C3MX1
C3MX2
0x7FFFFF
0x5A9DF7
0x7FFFFF
0x000000
0x000000
0x7FFFFF
0x400000
0x400000
UNUSED
5.13
Variable max power correction registers (addresses 0x27 to
0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
0
MPCC14
0
MPCC13
0
MPCC12
1
MPCC11
1
MPCC10
0
MPCC9
1
MPCC8
0
D7
D6
D5
D4
D3
D2
D1
D0
MPCC7
1
MPCC6
1
MPCC5
0
MPCC4
0
MPCC3
0
MPCC2
0
MPCC1
0
MPCC0
0
5.14
Variable distortion compensation registers (addresses 0x29
to 0x2A)
DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
D7
D6
D5
D4
D3
D2
D1
D0
DCC15
1
DCC14
1
DCC13
1
DCC12
1
DCC11
0
DCC10
0
DCC9
1
DCC8
1
49/54
STMICROELECTRONICS [ ST ]
