ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 4. ST92F150JDV1: Architectural Block Diagram
Ext. MEM.
ADDRESS
DATA
FLASH
128 Kbytes
A[7:0]
D[7:0]
Port0
3 TM
E
Ext. MEM.
ADDRESS
Ports 1,9
1K byte
A[21:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1]
P4[7:0]
P5[7:0]
P6[5:0]
P7[7:0]
P8[7:0]
P9[7:0]
RAM
6 Kbytes
AS
DS
RW
WAIT
NMI
DS2
RW
Fully Prog.
I/Os
256 bytes
Register File
8/16 bit
CPU
J1850
JBLPD
VPWI
VPWO
Interrupt
Management
INT[6:0]
WKUP[15:0]
ST9 CORE
2
SDA
SCL
I C BUS
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
RCCU
WDOUT
HW0SW1
WATCHDOG
MISO
MOSI
SCK
SS
CK_AF
STOUT
ST. TIMER
SPI
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
AV
AV
AIN[15:0]
EXTRG
DD
SS
ADC
EF TIMER 0
TXCLK
RXCLK
SIN
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
EF TIMER 1
DCD
SCI M
SCI A
SOUT
CLKOUT
RTS
TINPA0
TOUTA0
TINPB0
TOUTB0
MF TIMER 0
MF TIMER 1
RDI
TDO
TINPA1
TOUTA1
TINPB1
TOUTB1
RX0
TX0
CAN_0
CAN_1
VOLTAGE
REGULATOR
V
RX1
TX1
REG
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
8/426
1
STMICROELECTRONICS [ ST ]
