ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 3. ST92F150C(R/V)1/9: Architectural Block Diagram
FLASH
128/64 Kbytes
Ext. MEM.
ADDRESS
DATA
A[7:0]
D[7:0]
Port0
3 TM
E
1 Kbyte
Ext. MEM.
ADDRESS
Ports
A[10:8]
RAM
A[21:11]*
2/4 Kbytes
1,9*
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
AS
DS
RW
WAIT
NMI
DS2
RW*
Fully
Prog.
I/Os
256 bytes
Register File
8/16 bits
CPU
INT[5:0]
Interrupt
Management
INT6*
WKUP[13:0]
WKUP[15:14]*
P7[7:0]
P8[7:0]*
P9[7:0]*
ST9 CORE
RCCU
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
SDA
SCL
2
I C BUS
CK_AF
WDOUT
HW0SW1
ST. TIMER
STOUT
WATCHDOG
SPI
ICAPA0
OCMPA0
ICAPB0
OCMPB0*
EXTCLK0*
MISO
MOSI
SCK
SS
EF TIMER 0
AV
AV
AIN[15:8]
AIN[7:0]
EXTRG
DD
SS
ICAPA1
OCMPA1
ICAPB1
OCMPB1*
EXTCLK1*
ADC
EF TIMER 1
TXCLK
RXCLK
SIN
TINPA0
TOUTA0
TINPB0
MF TIMER 0
MF TIMER 1
DCD
SCI M
TOUTB0
SOUT
CLKOUT
RTS
TINPA1
TOUTA1
TINPB1
TOUTB1
RDI
TDO
SCI A*
CAN_0
VOLTAGE
REGULATOR
V
REG
RX0
TX0
* Not available on 64-pin version.
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8* and Port9*.
7/426
9
STMICROELECTRONICS [ ST ]
