ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 1. ST92F124R9: Architectural Block Diagram
FLASH
64 Kbytes
3 TM
E
P0[7:0]
P1[2:0]
P2[7:0]
P3[7:4]
P4[7:4]
P5[7:0]
P6[5:2,0]
P7[7:0]
1 Kbyte
Fully
Prog.
I/Os
RAM
2 Kbytes
NMI
256 bytes
Register File
8/16 bits
CPU
SDA
SCL
2
Interrupt
Management
I C BUS
INT[5:0]
WKUP[13:0]
ST9 CORE
RCCU
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
WDOUT
HW0SW1
WATCHDOG
MISO
MOSI
SCK
SS
CK_AF
ST. TIMER
STOUT
SPI
ICAPA0
OCMPA0
ICAPB0
EF TIMER 0
EF TIMER 1
AV
AV
AIN[15:8]
EXTRG
DD
SS
ADC
ICAPA1
OCMPA1
ICAPB1
TXCLK
RXCLK
SIN
TINPA0
TOUTA0
TINPB0
TOUTB0
SCI M
DCD
MF TIMER 0
MF TIMER 1
SOUT
CLKOUT
RTS
TINPA1
TOUTA1
TINPB1
TOUTB1
VOLTAGE
REGULATOR
V
REG
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6
and Port7.
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