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ST10F276S-4T3 参数 Datasheet PDF下载

ST10F276S-4T3图片预览
型号: ST10F276S-4T3
PDF下载: 下载PDF文件 查看货源
内容描述: 16位MCU与MAC单元832 KB的闪存和68 KB的RAM [16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM]
分类和应用: 闪存
文件页数/大小: 235 页 / 2491 K
品牌: STMICROELECTRONICS [ ST ]
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Internal Flash memory  
ST10F276E  
4.5  
Write operation examples  
In this section, examples for each kind of Flash write operation are presented.  
Word program  
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x0C5554 in XFLASH  
Module.  
FCR0H|= 0x2000; /*Set WPG in FCR0H*/  
FARL = 0x5554; /*Load Add in FARL*/  
FARH = 0x000C; /*Load Add in FARH*/  
FDR0L = 0xAAAA; /*Load Data in FDR0L*/  
FDR0H = 0xAAAA; /*Load Data in FDR0H*/  
FCR0H|= 0x8000; /*Operation start*/  
Double word program  
Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x095558 and  
data 0xAA55AA55 at address 0x09555C in IFLASH Module.  
FCR0H|= 0x1080; /*Set DWPG, SMOD*/  
FARL = 0x5558; /*Load Add in FARL*/  
FARH = 0x0009; /*Load Add in FARH*/  
FDR0L = 0x55AA; /*Load Data in FDR0L*/  
FDR0H = 0x55AA; /*Load Data in FDR0H*/  
FDR1L = 0xAA55; /*Load Data in FDR1L*/  
FDR1H = 0xAA55; /*Load Data in FDR1H*/  
FCR0H|= 0x8000; /*Operation start*/  
Double Word Program is always performed on the Double Word aligned on a even Word: bit  
ADD2 of FARL is ignored.  
Sector erase  
Example: Sector Erase of sectors B3F1 and B3F0 of Bank 3 in XFLASH Module.  
FCR0H|= 0x0800; /*Set SER in FCR0H*/  
FCR1H|= 0x0003; /*Set B3F1, B3F0*/  
FCR0H|= 0x8000; /*Operation start*/  
Suspend and resume  
Word Program, Double Word Program, and Sector Erase operations can be suspended in  
the following way:  
FCR0H|= 0x4000; /*Set SUSP in FCR0H*/  
Then the operation can be resumed in the following way:  
FCR0H|= 0x0800; /*Set SER in FCR0H*/  
FCR0H|= 0x8000; /*Operation resume*/  
Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is  
already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of  
Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise  
the operation is aborted and bit RESER of FER is set.  
42/235  
Doc ID 12303 Rev 3  
 
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