M93C86, M93C76, M93C66, M93C56, M93C46
Instructions
Figure 4.
READ, WRITE, WEN, WDS sequences
Read
S
D
Q
1 1 0 An
A0
Qn
Q0
ADDR
DATA OUT
OP
CODE
Write
S
D
Q
CHECK
STATUS
1 0 1 An
A0 Dn
D0
ADDR
DATA IN
BUSY
READY
OP
CODE
Write
Enable
S
D
Write
Disable
S
1 0 0 1 1 Xn X0
D
1 0 0 0 0 Xn X0
OP
OP
CODE
CODE
AI00878d
1. For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..
5.3
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in the READY/BUSY status
section.
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