Operation
M41T81
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is
shown in Figure 9 on page 12. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 6 on page 11 and again after it has received the word address and each data
byte.
2.4
Data retention mode
With valid V applied, the M41T81 can be accessed as described above with READ or
CC
WRITE Cycles. Should the supply voltage decay, the power input will be switched from the
V
pin to the battery when V falls below the Battery Back-up Switchover Voltage (V ).
CC
CC SO
At this time the clock registers will be maintained by the attached battery supply. On power-
up, when V returns to a nominal value, write protection continues for t (see Figure 10
CC
rec
on page 23, Table 11 on page 24).
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
Figure 9.
WRITE mode sequence
BBUSUSACATICVTITIYV:ITY:
MMASATSETRER
WORD
ADDRESS (An)
SDA LINE
SDA LINE
S
DATA n
DATA n+1
DATA n+1
DATA n+X
P
S
DATA n
DATA n+X
P
BBUSUSACATICVTITIYV:ITY:
SLAVE
ADDRSESLSAVE
AI00591
ADDRESS
AI00895
12/30
STMICROELECTRONICS [ ST ]
