Operation
M41T81
Figure 4.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 5.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T81 slave after setting the slave address (see
Figure 7 on page 11). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge
Bit, the word address 'An' is written to the on-chip address pointer. Next the START
condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1).
At this point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an Acknowledge Bit to the
slave transmitter. The address pointer is only incremented on reception of an Acknowledge
Clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a Stop Condition or when the
pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ Mode and WRITE Mode.
10/30
STMICROELECTRONICS [ ST ]
