欢迎访问ic37.com |
会员登录 免费注册
发布采购

M41T81M6F 参数 Datasheet PDF下载

M41T81M6F图片预览
型号: M41T81M6F
PDF下载: 下载PDF文件 查看货源
内容描述: 报警串行访问实时时钟 [Serial access Real-Time Clock with alarm]
分类和应用: 时钟
文件页数/大小: 30 页 / 303 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号M41T81M6F的Datasheet PDF文件第4页浏览型号M41T81M6F的Datasheet PDF文件第5页浏览型号M41T81M6F的Datasheet PDF文件第6页浏览型号M41T81M6F的Datasheet PDF文件第7页浏览型号M41T81M6F的Datasheet PDF文件第9页浏览型号M41T81M6F的Datasheet PDF文件第10页浏览型号M41T81M6F的Datasheet PDF文件第11页浏览型号M41T81M6F的Datasheet PDF文件第12页  
Operation  
M41T81  
2
Operation  
The M41T81 clock operates as a slave device on the serial bus. Access is obtained by  
implementing a start condition followed by the correct slave address (D0h). The 20 bytes  
contained in the device can then be accessed sequentially in the following order:  
st  
1 Byte: tenths/hundredths of a second register  
nd  
2
3
Byte: seconds register  
Byte: minutes register  
rd  
th  
4 Byte: century/hours register  
th  
5 Byte: day register  
th  
6 Byte: date register  
th  
7 Byte: month register  
th  
8 Byte: year register  
th  
9 Byte: control register  
th  
10 Byte: watchdog register  
th  
th  
11 - 16 Bytes: alarm registers  
th  
th  
17 - 19 Bytes: reserved  
th  
20 Byte: square wave register  
The M41T81 clock continually monitors V for an out-of-tolerance condition. Should V  
CC  
CC  
fall below V , the device terminates an access in progress and resets the device address  
SO  
counter. Inputs to the device will not be recognized at this time to prevent erroneous data  
from being written to the device from a an out-of-tolerance system. The device also  
automatically switches over to the battery and powers down into an ultra low current mode  
of operation to conserve battery life. As system power returns and V rises above V , the  
CC  
SO  
battery is disconnected, and the power supply is switched to external V  
.
CC  
For more information on Battery Storage Life refer to Application Note AN1012.  
2.1  
2-wire bus characteristics  
The bus is intended for communication between different ICs. It consists of two lines: a bi-  
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be  
connected to a positive supply voltage via a pull-up resistor.  
The following protocol has been defined:  
Data transfer may be initiated only when the bus is not busy.  
During data transfer, the data line must remain stable whenever the clock line is High.  
Changes in the data line, while the clock line is High, will be interpreted as control  
signals.  
Accordingly, the following bus conditions have been defined:  
2.1.1  
Bus not busy  
Both data and clock lines remain High.  
8/30  
 复制成功!