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M25P16-VMW6TG 参数 Datasheet PDF下载

M25P16-VMW6TG图片预览
型号: M25P16-VMW6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,低电压,串行闪存,具有50 MHz SPI总线接口 [16 Mbit, low voltage, Serial Flash memory with 50 MHz SPI bus interface]
分类和应用: 闪存存储
文件页数/大小: 55 页 / 488 K
品牌: STMICROELECTRONICS [ ST ]
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DC and AC parameters  
M25P16  
Table 15. AC characteristics (Grade 6)  
Test conditions specified in Table 10 and Table 12  
Symbol Alt.  
Parameter  
Min.  
Typ.  
Max. Unit  
Clock Frequency(1) for the following instructions: FAST_READ,  
PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR  
fC  
fR  
fC  
D.C.  
50  
20  
MHz  
Clock Frequency for READ instructions  
D.C.  
9
MHz  
ns  
(1)  
tCH  
tCLH Clock High Time  
tCLL Clock Low Time  
(1)  
tCL  
9
ns  
(2)  
(2)  
tCLCH  
Clock Rise Time(3) (peak to peak)  
0.1  
0.1  
5
V/ns  
V/ns  
ns  
tCHCL  
Clock Fall Time(3) (peak to peak)  
tCSS S Active Setup Time (relative to C)  
S Not Active Hold Time (relative to C)  
tDSU Data In Setup Time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
5
ns  
2
ns  
tDH Data In Hold Time  
5
ns  
S Active Hold Time (relative to C)  
S Not Active Setup Time (relative to C)  
tCSH S Deselect Time  
5
ns  
5
ns  
100  
ns  
(2)  
tSHQZ  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tDIS Output Disable Time  
8
8
ns  
tV  
tHO Output Hold Time  
HOLD Setup Time (relative to C)  
Clock Low to Output Valid  
ns  
0
5
5
5
5
ns  
ns  
HOLD Hold Time (relative to C)  
HOLD Setup Time (relative to C)  
ns  
ns  
HOLD Hold Time (relative to C)  
ns  
(2)  
tHHQX  
tLZ HOLD to Output Low-Z  
8
8
ns  
(2)  
tHLQZ  
tWHSL  
tSHWL  
tHZ HOLD to Output High-Z  
ns  
(4)  
(4)  
Write Protect Setup Time  
20  
ns  
Write Protect Hold Time  
100  
ns  
(2)  
tDP  
tRES1  
tRES2  
tW  
S High to Deep Power-down Mode  
S High to Standby Mode without Electronic Signature Read  
S High to Standby Mode with Electronic Signature Read  
Write Status Register Cycle Time  
Page Program Cycle Time (256 Bytes)  
3
µs  
(2)  
(2)  
30  
30  
15  
µs  
µs  
5
ms  
1.4  
(5)  
tPP  
5
ms  
0.4+  
n*1/256  
Page Program Cycle Time (n Bytes)  
tSE  
tBE  
Sector Erase Cycle Time  
Bulk Erase Cycle Time  
1
3
s
s
17  
40  
1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one  
sequence including all the Bytes versus several sequences of only a few Bytes. (1 n 256)  
40/55  
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