DC and AC parameters
Table 9.
M24C16-125 M24C08-125 M24C04-125 M24C02-125
2
AC characteristics at 400 kHz (I C Fast mode)
Test conditions specified in Section 6: DC and AC parameters
Min.(1) Max.(1)
Symbol
Alt.
fSCL
Parameter
Unit
fC
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
tHIGH Clock pulse width high
tLOW Clock pulse width low
600
-
-
1300
tQL1QL2
tF
tR
tF
SDA (out) fall time
Input signal rise time
Input signal fall time
20(3)
120
(2)
(4)
(4)
tXH1XH2
tXL1XL2
tDXCX
(4)
(4)
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(5)
tCLQX
tDH
tAA
Data out hold time
100
200
600
600
600
-
(6)
tCLQV
Clock low to next data valid (access time)
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
1300
-
-
ns
Write time
5
ms
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 4.
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STMICROELECTRONICS [ ST ]
