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M24C01-WMN6TP/S 参数 Datasheet PDF下载

M24C01-WMN6TP/S图片预览
型号: M24C01-WMN6TP/S
PDF下载: 下载PDF文件 查看货源
内容描述: 16Kbit的, 8Kbit , 4k位, 2Kbit和1K位,串行I²C总线EEPROM [16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 25 页 / 451 K
品牌: STMICROELECTRONICS [ ST ]
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M24C16, M24C08, M24C04, M24C02, M24C01  
Figure 10. Read Mode Sequences  
ACK  
NO ACK  
DATA OUT  
CURRENT  
ADDRESS  
READ  
DEV SEL  
R/W  
ACK  
ACK  
ACK  
NO ACK  
DATA OUT  
RANDOM  
ADDRESS  
READ  
DEV SEL *  
BYTE ADDR  
DEV SEL *  
R/W  
R/W  
ACK  
ACK  
ACK  
NO ACK  
DATA OUT N  
SEQUENTIAL  
CURRENT  
READ  
DEV SEL  
DATA OUT 1  
R/W  
ACK  
ACK  
ACK  
ACK  
SEQUENTIAL  
RANDOM  
READ  
DEV SEL *  
BYTE ADDR  
DEV SEL * DATA OUT 1  
R/W  
R/W  
ACK  
NO ACK  
DATA OUT N  
AI01942  
st  
rd  
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.  
Read Operations  
Read operations are performed independently of  
the state of the Write Control (WC) signal.  
dressed byte. The bus master must not  
acknowledge the byte, and terminates the transfer  
with a Stop condition.  
Current Address Read  
The device has an internal address counter which  
is incremented each time a byte is read.  
Random Address Read  
A dummy Write is first performed to load the ad-  
dress into this address counter (as shown in Fig-  
ure 10.) but without sending a Stop condition.  
Then, the bus master sends another Start condi-  
tion, and repeats the Device Select Code, with the  
Read/Write bit (RW) set to 1. The device acknowl-  
edges this, and outputs the contents of the ad-  
For the Current Address Read operation, following  
a Start condition, the bus master only sends a De-  
vice Select Code with the Read/Write bit (RW) set  
to 1. The device acknowledges this, and outputs  
the byte addressed by the internal address  
counter. The counter is then incremented. The bus  
master terminates the transfer with a Stop condi-  
tion, as shown in Figure 10., without acknowledg-  
ing the byte.  
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