Registers description
LIS3DH
8.19
FIFO_CTRL_REG (2Eh)
Table 42. REFERENCE register
FM1 FM0 TR
FTH4
FTH3
FTH2
FTH1
FTH0
Table 43. REFERENCE register description
FM1-FM0
FIFO mode selection. Default value: 00 (see Table 44)
TR
Trigger selection. Default value: 0
0: Trigger event liked to trigger signal on INT1
1: Trigger event liked to trigger signal on INT2
FTH4:0
Default value: 0
Table 44. FIFO mode configuration
FM1 FM0
Self test mode
0
0
1
1
0
1
0
1
Bypass mode
FIFO mode
Stream mode
Trigger mode
8.20
8.21
FIFO_SRC_REG (2Fh)
Table 45. FIFO_SRC register
WTM
OVRN_FIFO
EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
INT1_CFG (30h)
Table 46. INT1_CFG register
AOI
6D
ZHIE/
ZUPE
ZLIE/
YHIE/
YUPE
YLIE/
YDOWNE
XHIE/
XUPE
XLIE/
ZDOWNE
XDOWNE
Table 47. INT1_CFG description
AOI
And/Or combination of Interrupt events. Default value: 0. Refer to Table 48, "Inter-
rupt mode"
6D
6 direction detection function enabled. Default value: 0. Refer to Table 48, "Interrupt
mode"
ZHIE/
ZUPE
Enable interrupt generation on Z high event or on Direction recognition. Default
value: 0 (0: disable interrupt request;1: enable interrupt request)
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Doc ID 17530 Rev 1
STMICROELECTRONICS [ ST ]
