Registers description
LIS3DH
ODR<3:0> is used to set power mode and ODR selection. In the following table are reported
all frequency resulting in combination of ODR<3:0>
Table 26. Data rate configuration
ODR3
ODR2
ODR1
ODR0
Power mode selection
Power down mode
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Normal / low power mode (1 Hz)
Normal / low power mode (10 Hz)
Normal / low power mode (25 Hz)
Normal / low power mode (50 Hz)
Normal / low power mode (100 Hz)
Normal / low power mode (200 Hz)
Normal / low power mode (400 Hz)
Low power mode (1.6 KHz)
Normal (1.25 kHz) / low power mode (5 KHz)
8.9
CTRL_REG2 (21h)
Table 27. CTRL_REG2 register
HPM1 HPM0 HPCF2
HPCF1
FDS
HPCLICK
HPIS2
HPIS1
Table 28. CTRL_REG2 description
HPM1 -HPM0 High pass filter mode selection. Default value: 00
Refer to Table 29, "High pass filter mode configuration"
HPCF2 -
High pass filter cut off frequency selection
HPCF1
Filtered data selection. Default value: 0
FDS
(0: internal filter bypassed; 1: data from internal filter sent to output register and
FIFO)
High pass filter enabled for CLICK function.
(0: filter bypassed; 1: filter enabled)
HPCLICK
HPIS2
High pass filter enabled for AOI function on interrupt 2,
(0: filter bypassed; 1: filter enabled)
HPIS1
High pass filter enabled for AOI function on interrupt 1,
(0: filter bypassed; 1: filter enabled)
30/42
Doc ID 17530 Rev 1
STMICROELECTRONICS [ ST ]
