LIS3DH
Registers description
Table 29. High pass filter mode configuration
HPM1
HPM0
High pass filter mode
0
0
1
1
0
1
0
1
Normal mode (reset reading HP_RESET_FILTER)
Reference signal for filtering
Normal mode
Autoreset on interrupt event
8.10
CTRL_REG3 (22h)
Table 30. CTRL_REG3 register
I1_CLICK I1_AOI1
I1_AOI2
I1_DRDY1 I1_DRDY2
I1_WTM
I1_OVERRUN
--
Table 31. CTRL_REG3 description
I1_CLICK
I1_AOI1
CLICK interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
AOI1 interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
I1_AOI2
AOI2 interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
I1_DRDY1
I1_DRDY2
I1_WTM
DRDY1 interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
DRDY2 interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
FIFO Watermark interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
I1_OVERRUN
FIFO Overrun interrupt on INT1. Default value 0.
(0: Disable; 1: Enable)
8.11
CTRL_REG4 (23h)
Table 32. CTRL_REG4 register
BDU
BLE
FS1
FS0
HR
ST1
ST0
SIM
Table 33. CTRL_REG4 description
BDU
Block data update. Default value: 0
(0: continuos update; 1: output registers not updated until MSB and LSB
reading)
BLE
Big/little endian data selection. Default value 0.
(0: Data LSB @ lower address; 1: Data MSB @ lower address)
FS1-FS0
Full scale selection. default value: 00
(00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G)
Doc ID 17530 Rev 1
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STMICROELECTRONICS [ ST ]
