FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
12.0 POWER-SAVING MODES
12.2 Power-down Mode
The power-down mode is entered by setting the PD bit in
the PCON register. In the power-down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupts only. SRAM contents are retained during power-
down, the minimum VDD level is 2.0V.
The device provides two power saving modes of operation
for applications where power consumption is critical. The
two modes are idle and power-down, see Table 12-1.
12.1 Idle Mode
The device exits power-down mode through either an
enabled external level sensitive interrupt or a hardware
reset. The start of the interrupt clears the PD bit and exits
power-down. Holding the external interrupt pin low restarts
the oscillator, the signal must hold low at least 1024 clock
cycles before bringing back high to complete the exit. Upon
interrupt signal being restored to logic VIH, the first instruc-
tion of the interrupt service routine will execute. A hardware
reset starts the device similar to power-on reset.
Idle mode is entered setting the IDL bit in the PCON regis-
ter. In idle mode, the program counter (PC) is stopped. The
system clock continues to run and all interrupts and periph-
erals remain active. The on-chip RAM and the special func-
tion registers hold their data during this mode.
The device exits idle mode through either a system inter-
rupt or a hardware reset. Exiting idle mode via system
interrupt, the start of the interrupt clears the IDL bit and
exits idle mode. After exit the Interrupt Service Routine, the
interrupted program resumes execution beginning at the
instruction immediately following the instruction which
invoked the idle mode. A hardware reset starts the device
similar to a power-on reset.
To exit properly out of power-down, the reset or external
interrupt should not be executed before the VDD line is
restored to its normal operating voltage. Be sure to hold
VDD voltage long enough at its normal operating level for
the oscillator to restart and stabilize (normally less than
10 ms).
TABLE 12-1: Power Saving Modes
Mode
Initiated by
State of MCU
CLK is running.
Exited by
Idle Mode
Software
Enabled interrupt or hardware reset.
(Set IDL bit in PCON)
MOV PCON, #01H;
Interrupts, serial port and tim- Start of interrupt clears IDL bit and
ers/counters are active. Pro- exits idle mode, after the ISR RETI
gram Counter is stopped.
ALE and PSEN# signals at a tion beginning at the instruction follow-
HIGH level during Idle. All ing the one that invoked idle mode. A
instruction, program resumes execu-
registers remain unchanged. user could consider placing two or
three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware
reset restarts the device similar to a
power-on reset.
Power-down
Mode
Software
(Set PD bit in PCON)
MOV PCON, #02H;
CLK is stopped. On-chip
SRAM and SFR data is main- rupt or hardware reset. Start of inter-
tained. ALE and PSEN# sig- rupt clears PD bit and exits power-
Enabled external level sensitive inter-
nals at a LOW level during
down mode, after the ISR RETI
power -down. External Inter- instruction program resumes execution
rupts are only active for level beginning at the instruction following
sensitive interrupts, if
enabled.
the one that invoked power-down
mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes power-down
mode to eliminate any problems. A
hardware reset restarts the device sim-
ilar to a power-on reset.
T12-1.0 1273
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
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SST [ SILICON STORAGE TECHNOLOGY, INC ]
