8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Data# Polling (DQ7)
General Purpose Inputs Register
When the SST49LF008A device is in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. Proper status will not be given using Data# Polling if the
address is in the invalid range.
The GPI_REG (General Purpose Inputs Register) passes
the state of FGPI[4:0] pins at power-up on the
SST49LF008A. It is recommended that the FGPI[4:0] pins
are in the desired state before FWH4 is brought low for the
beginning of the bus cycle, and remain in that state until the
end of the cycle. There is no default value since this is a
pass-through register. The GPI register for the boot device
appears at FFBC0100H in the 4 GByte system memory
map, and will appear elsewhere if the device is not the boot
device. Register is not available for read when the device is
in Erase/Program operation. See Table 5 for the GPI_REG
bits and function.
TABLE 5: General Purpose Inputs Register
Toggle Bit (DQ6)
Pin #
Bit Function
32-PLCC 32-TSOP 40-TSOP
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating
‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the
internal Program or Erase operation is completed, the
toggling will stop.
7:5 Reserved
-
-
-
4
3
2
1
0
FGPI[4]
Reads status of general
purpose input pin
30
6
7
FGPI[3]
Reads status of general
purpose input pin
3
4
5
6
11
12
13
14
15
16
17
Multiple Device Selection
FGPI[2]
Reads status of general
purpose input pin
The four ID pins, ID[3:0], allow multiple devices to be
attached to the same bus by using different ID strapping in
a system. When the SST49LF008A is used as a boot
device, ID[3:0] must be strapped as 0000, all subsequent
devices should use a sequential up-count strapping (i.e.
0001, 0010, 0011, etc.). The SST49LF008A will compare
the strapping values, if there is a mismatch, the device will
ignore the remainder of the cycle and go into standby
mode. For further information regarding FWH device map-
ping and paging, please refer to the Intel 82801(ICH) I/O
Controller Hub documentation. Since there is no ID support
in PP Mode, to program multiple devices a stand-alone
PROM programmer is recommended.
FGPI[1]
Reads status of general
purpose input pin
FGPI[0]
Reads status of general
purpose input pin
18
T5.3 1161
Block Locking Registers
SST49LF008A provides software controlled lock pro-
tection through a set of Block Locking registers. The
Block Locking Registers are read/write registers and it
is accessible through standard addressable memory
locations specified in Table 6. Unused register loca-
tions will read as 00H.
REGISTERS
There are three types of registers available on the
SST49LF008A, the General Purpose Inputs register, Block
Locking registers and the JEDEC ID registers. These regis-
ters appear at their respective address location in the 4
GByte system memory map. Unused register locations will
read as 00H. Attempts to read or write to any registers dur-
ing internal Write operations will be ignored.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
15
SST [ SILICON STORAGE TECHNOLOGY, INC ]
